发明名称 Insulation method for integrated circuits, in particular with MOS and CMOS devices.
摘要 <p>An insulation method integrated circuits, in particular with MOS and CMOS devices, reducing the minimum distance between the active regions up to the lithographic limit, regardless of the geometry of the field areas, comprises forming, in a semiconductor substrate, trenches having a reduced width, which delimit the active regions of the circuit and the extended field areas, filling the trenches with insulating material and local surface oxidating the field areas.</p>
申请公布号 EP0245783(A2) 申请公布日期 1987.11.19
申请号 EP19870106645 申请日期 1987.05.07
申请人 SGS MICROELETTRONICA S.P.A. 发明人 CAPPELLETTI, PAOLO GIUSEPPE
分类号 H01L27/08;H01L21/76;H01L21/762;H01L21/763;H01L29/78 主分类号 H01L27/08
代理机构 代理人
主权项
地址