发明名称 CMOS MASTER SLICE LSI
摘要 PURPOSE:To improve the integration density of a random logic circuit, by constituting a basic cell by one or two p-channel transistors and two n-channel transistors, making the width of said p-and n-channel transistors to be the smallest, thereby reducing the change in number of wiring bands, and reducing the number of unused wirings. CONSTITUTION:A numeral 1 indicates a p-channel transistor column, a numeral 2 indicates an n-channel transistor column and a numeral 3 indicates wiring bands. A basic cell is constituted by one p-channel transistor and two n-channel transistors. The width of the p-and n-channel transistors is made to be the smallest in a degree the formation of a macro-cell is not hampered. In the (p) channel(width of 17mum), 9 pieces of wirings can be provided. In the (n) channel(width of 14mum), 6 pieces of wirings can be provided. The wirings in the wiring band can be made to be the numbers of 6, 9, 12....The change in number of the wirings is made small, and the unused wirings can be reduced.
申请公布号 JPS62266849(A) 申请公布日期 1987.11.19
申请号 JP19860111559 申请日期 1986.05.14
申请人 MITSUBISHI ELECTRIC CORP 发明人 KURAMITSU YOICHI;UEDA MASAHIRO;ARAKAWA TAKAHIKO
分类号 H01L27/092;H01L21/82;H01L21/8234;H01L21/8238;H01L27/088;H01L27/118 主分类号 H01L27/092
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