| 摘要 |
PURPOSE:To speed up operation by providing a zero detection circuit so as to detect the zero of a partial remainder, and resetting a flag. CONSTITUTION:A logical operation device 3 subtracts a divisor register 2 from the reading of a dividend register 1, and stores the result in a partial remainder register 4. At such a time, the carry bit of said register 4 is decided either '0' or '1', and if it is '0', an operation result register 5 is shifted left by one bit, and '1' is transmitted to a bit G in the logical operation register 5. If the carry bit is '1', said register 5 is shifted left by one bit, and '1' is transmitted to the bit G. Then, the contents of the partial remainder register 4 is shifted left by one bit, and transferred to the dividend register 1, and the next operation of the dividend and the divisor is made a subtraction. If the dividend is exactly divisible upon the completion or in the middle of operation, an OR gate 6 connected to the partial remainder register 4 detects that the partial remainder is zero, and a bit S initialized to '1' by an FF 7 is reset to '0', whereby that the dividend is divisible is shown. |
