| 摘要 |
PURPOSE:To convert an input pulse into a pulse whise duty is 1:1 without causing malfunction by using an inverter to invert an input pulse, ANDing an output of a 1/(2n+1) frequency division circuit and an inverter output so as to set or reset a shift register. CONSTITUTION:A 1/3 frequency division circuit 20 applies 1/3 frequency division to an input pulse (a) to output a pulse (b) whose duty is 1:2 synchronously with the positive leading edge of the input pulse (a) from an output terminal Q1. An AND circuit 4 ANDs the output of the 1/3 frequency division circuit 20 and the output of the inverter 3, outputs a pulse C, which is given to a set terminal S of a shift register 5. The shift register 5 shifts the output of the 1/3 frequency division circuit 20 for one period of the input pulse (a) synchronously with the positive leading edge of the input pulse (a), and since the output of the AND circuit 4 is given to the set terminal S of the shift register 5, a pulse (d) whose frequency is 1/3 of the frequency of the input pulse (a) and whose duty is 1:1 is outputted from the output terminal Q2 of the shift register 5. |
