发明名称 COMPLEMENTARY DIGITAL LOGIC CIRCUIT
摘要 PURPOSE:To use a complementary MESFET digital circuit with low power consumption, high-power voltage and large amplitude by applying the separate control of a gate voltage to p-channel and n-channel FETs. CONSTITUTION:When a voltage 0V is applied to the input of the titled circuit, diodes in a level shift circuit comprising a resistor R1 and diodes D1-D4 is biased forward, a gate voltage of a transistor (TR) 1 (p-channel MESFET) is 4V equivalent to the forward voltage of four diodes, then the TR l is conductive. The gate voltage of a TR 2 (n-channel MESFET) is clearly 0V, the TR 2 is cut off and then a voltage of 5V is outputted. In inputting the voltage 5V to the circuit, the gate voltage of the TR1 is 5V and the TR1 is cut off. The diodes of the level shift circuit comprising a resistor R2 and diodes D5-D8 are biased forward, the gate voltage of the TR 2 is 1V obtained by subtracting 4V from the voltage 5V, the TR 2 is conductive and the output is 0V.
申请公布号 JPS62260425(A) 申请公布日期 1987.11.12
申请号 JP19860103531 申请日期 1986.05.06
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 MATSUDA KAZUHIRO;FUKUDA HIDEKI
分类号 H03K19/08;H03K19/0948 主分类号 H03K19/08
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