| 摘要 |
PURPOSE:To shorten the access time with a main memory controller by providing a path to set the correction data received from an error detection/correction circuit directly to a write data buffer and therefore writing and reading collectively the correction data to and out of a main memory after a series of data are read out. CONSTITUTION:The data 1 is read out of a main memory and set to a read data latch RDL2. Then the data 1 is checked by an error detection/correction circuit EDC3 and at the same time the next data 2 is set to a read data latch RDL2 for reading. An error of the data if detected is corrected by the EDC3 and the corrected data is sent to an external processor via a read data buffer RDB4 as well as to a write data buffer WDB5. While the EDC3 checks the data 2. The correction data on the WDB5 are collectively written to the main memory via a write data latch WDL6 after a series of data are delivered.
|
