Circuit arrangement for simulating an inductance

摘要

For simulating an inductance (L) by electronic means, a field-effect transistor (F) constructed as controlling transistor is used, the drain-source voltage of which is statically controlled to a predetermined voltage. The predetermined voltage is selected to be less than the gate-source threshold voltage of the field-effect transistor (F). This arrangement has very little power dissipation and is suitable for use as input reactor for pulse-frequency-modulated low-power switched-mode controllers (Fig. 1). <IMAGE>