| 摘要 |
PURPOSE:To obtain an address generating circuit that can decrease the number of instruction steps produced by the generation of addresses, by deciding with control whether the code extension of an offset address supplied to an adder should be carried out or not. CONSTITUTION:When an index operation filed IDX is equal to '00', the address qualification data (i) is held as it is in a selection field IX24 and an offset address A is outputted as it is to the contents of a generated address. Then the address value AD2 with which the codes of the address A are infinite is outputted to an output terminal 22. When the field IDX is equal to '01', an adder 23 is set under an inhibition mode with the input of the address A. Thus the adder 23 performs an addition (i+AD2) and outputs it. Then the adder 23 is set under a code extension mode with IDX=10 and regards the address A as a number having a code. Thus the code is extended up to the bit length equal to (i) and the adder 23 performs an addition (i+A=i+AS.AD1) and outputs it. When IDX=11 is satisfied, the same addition as that carried out in a mode of IDX=10 is performed and outputted via a selector 26. At the same time, the addition is set again to the field IX24 via a selector 25 for the updating of indexes.
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