| 摘要 |
PURPOSE:To allow a logic circuit to detect the frequency of an input signal by adopting a synchronizing sequential logic circuit constitution using a D-FF and a JK-FF. CONSTITUTION:D-FF 11, 13, 19 and a JK-FF 16 are used to constitute the synchronizing sequential logic circuit satisfying equation. When the frequency of an input signal is 1/2 time of the horizontal scanning frequency fH, the 1st logic level detection signal is outputted. When the input signal frequency is fH/3, the detection signal of the 2nd logic level is outputted. Further, when the input signal frequency is fH, a pulse taking the level being l/2 of the level of the 1st and 2nd logic levels as a mean value is outputted as a detection signal. When the frequency is fH/2, the level of 1/2 or 3/4 time of the difference level as the mean value is outputted as the detection signal.
|
