| 摘要 |
PURPOSE:To uniformly and surely correct a parity error without arranging two memories generating soft errors in the lines or rows of a matrix even if the errors are simultaneously generated by successively arraying memory cells connected to the same word line in the diagonal direction of a virtual matrix. CONSTITUTION:Memory cells 401 connected to a work line 107 are successively arrayed in the diagonal direction of the virtual matrix, parity cells 501, 502 are made to correspond to horizontal and vertical memory cell groups and the horizontal and vertical parity contents are stored in an H cell 501 and a V cell 502 as check information. In the addresses of the virtual matrix of the memory cells, the upper left is (1, 1) and the lower right is (4, 4). If the data of the cells in (1, 4) and (2, 3) are simultaneously changed to '0', the parity check of H1 is executed, V4-V1 are successively checked and then V4-V1 in H2 are successively selected 108, 109 and checked 110, 111 and correction 113 corresponding to an error is executed through an AND gate 112. Thereby, two adjacent errors are surely corrected.
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