发明名称 |
CIRCUIT DEVICEGENERATING CLOCK SIGNAL |
摘要 |
Circuit arrangement for generating a clock signal which is rigidly locked to the line frequency, for decoding digitised television signals. The clock frequency is generated with the aid of a first PLL circuit which receives as reference frequency the reference frequency generated with the aid of a second PLL circuit, which is locked to the line frequency. |
申请公布号 |
JPS62258571(A) |
申请公布日期 |
1987.11.11 |
申请号 |
JP19870024912 |
申请日期 |
1987.02.06 |
申请人 |
DEUTSCHE THOMSON BRANDT GMBH |
发明人 |
AKUSERU PIIRE BERURANTO;JIYAN KURAUDE RUFURAI |
分类号 |
H04N7/26;H03L7/08;H04N5/06;H04N7/025;H04N7/03;H04N7/035;H04N9/44 |
主分类号 |
H04N7/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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