DIGITAL SIGNAL PROCESSOR

摘要

PURPOSE:To speed up digital signal processing by forming hierarchical constitution with digital signal processors DSP I and II and forming mutually a one- dimensional array of element processors of arithmetic and I/O ports for the DSP II. CONSTITUTION:The DSP I sets previously the start address of a data buffer 4 and control information on gates 9-11 and bidirectional drivers 7 and 8 for actuation of plural element processors PE. Then the DSP I reads input data 24 out of a data buffer I to supply it to a PE5-1 via a connection 23-0 and at the same time controls the PE5-1-5-M via a connection 22. In this case the start timing of a port register II is shifted and therefore the pipeline processing is carried out between those PE. Thus each PE starts its autonomous action and stores the arithmetic result in a buffer II via the PE5-1 or 5-M. Thus the arithmetic result is shifted to the DSP I through the prescribed bits of a connection 30-1 and an output port register 3-3.