发明名称 PROCESSING SYSTEM FOR INSTRUCTION SCHEDULING
摘要 PURPOSE:To decrease the interlocking frequency of a pipeline and to increase the executing speed of an object program, by performing the instruction scheduling in a conversion mode in consideration of an instruction group to be carried out between blocks immediately before and after the block. CONSTITUTION:The object code converting part 23 of a compiler 2 converts the intermediate text groups 61 and 62 included in an intermediate text 6 into object codes 71 and 72 in consideration of the instruction group to be carried out immediately before and after a block. In other words, the instruction defining a register SO contained in a code 71 is shifted to the position before the instruction which does not define the register SO that is practicable after the instruction which defines the register SO via the instruction scheduling process since an instruction using the register SO is included in the instruction group contained in the block to be executed immediately after the instruction. In the same way, the instruction using the register SO contained in the code 72 is shifted to the position after the instruction which uses no register SO since the instruction that defines the register SO is included in the instruction group contained in the block to be executed immediately before the instruction.
申请公布号 JPS62259142(A) 申请公布日期 1987.11.11
申请号 JP19860102729 申请日期 1986.05.02
申请人 NEC CORP 发明人 KANEKO TAKASHI
分类号 G06F9/38;G06F9/44;G06F9/45 主分类号 G06F9/38
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