发明名称 GATE ARRAY CIRCUIT
摘要 PURPOSE:To utilize the area of a chip effectively by arranging an external terminal and an input/output circuit section to one side of the chip and the opposite side oppositely faced to one side of the chip and disposing an internal circuit section between the array of one side and the opposite side. CONSTITUTION:Gate array circuits 1 are arranged onto a wafer. The circuit 1 represents a minimum circuit unit, a plurality of external terminals 2 and input/output circuits 3 are arrayed along upper and lower sides, and an internal circuit section region 4 is disposed between the upper and lower arrangements. The circuits 1 as each minimum circuit unit are disposed repeatedly at the intervals of the cutting clearances 5 of chips. A gate-array-chip is organized by connecting n-circuits 1 as the minimum circuit units, a chip 6 represents one minimum circuit, and a chip 7 represents the constitution of two minimum circuit units. According to such constitution, the areas of the chips 6, 7 can be utilized effectively, and foundations need not be reconstructed in response to the terminals 2, the circuits 3 and the regions 4.
申请公布号 JPS62257748(A) 申请公布日期 1987.11.10
申请号 JP19860100499 申请日期 1986.04.30
申请人 NEC CORP 发明人 OUCHI YASUNORI
分类号 H01L21/82;H01L21/822;H01L27/04;H01L27/118 主分类号 H01L21/82
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