发明名称 SUPERVISORY TIMER CONTROL SYSTEM
摘要 PURPOSE:To eliminate interruption caused by an unnecessary overflow of a supervisory timer while debugging a program, by suppressing the operation of the supervisory time in response to an external command. CONSTITUTION:When an instruction control means is actuated, the means first discriminates whether the key code is the start key or stop key by means of a key code analysing section 31. When the key code is the stop key, a supervisory timer updating suppressing section 32 is operated and '0' is set at a flip flop 12 through a diagnostic interface 3. Accordingly, a gate circuit 11 is closed and the clock from a clock oscillator 13 is not supplied to a supervisory timer 10 and, as a result, updating of the timer 10 is suppressed. When the updating suppression/release of the supervisory timer 10 is caused to be made through the stop/start of an instruction in such way, interruption caused by an unnecessary overflow of the supervisory timer while debugging a program can be eliminated.
申请公布号 JPS62257545(A) 申请公布日期 1987.11.10
申请号 JP19860101462 申请日期 1986.05.01
申请人 NEC CORP 发明人 MORISAWA SHIGEAKI
分类号 G06F11/30 主分类号 G06F11/30
代理机构 代理人
主权项
地址