| 摘要 |
PURPOSE:To eliminate erroneous operation due to various sounds or noise, etc. and to exactly detect a vertical synchronizing signal with high accuracy by prohibiting the action of an AND circuit for a time approximately equal to the period of a vertical synchronizing signal. CONSTITUTION:A vertical synchronizing separator circuit 1 separates a vertical synchronizing signal (b) of a period V from a composite synchronizing signal (a). A counter circuit 3 counts the oscillating output of a period shorter than the period V of an oscillator 4, and when the counting reaches a prescribed value, transmits a counting output (d) to the AND gate circuit 2 so that an AND output (e) is transmitted to a terminal B as a vertical synchronizing signal. The counter circuit 3 is reset by the AND output of the vertical synchronizing signal C(b) and its own counting output (d), and prohibits the AND output of the AND gate circuit 2 for a period T. In case a composite synchronizing signal (a) including a noise pulse 5 occurred during the duration of a horizontal synchronizing signal is inputted, since an erroneous detection output 6 occurrs within the duration of the prohibiting time T, the output 6 is not outputted from the AND gate circuit 2, hence the vertical synchronizing signal (e) outputed is not influenced by the noise pulse 5. |
