| 摘要 |
PURPOSE:To effectively prevent a simultaneous access, to improve a software performance and to assure data by providing an IRQ generating circuit and a timing shift circuit. CONSTITUTION:Write data transmitted from a processor 20 is temporarily stored in a write buffer 02, the IRQ generating circuit 04 is activated by a write signal transmitted from the processor 20, to perform an interruption to a processor 06, as a result of this, the data previously written in a register 05 between processor is read by a read signal 17 outputted by the processor 06, the write signal 13 is outputted to the write buffer 02 in the timing of this read signal and the next data is written in the register 05 between processors. Thereby, the simultaneous access can be prevented. |
