| 摘要 |
PURPOSE:To prevent a short width noise included in an input signal, if any, from appearing at an output by using three flip-flops so as to give a common clock input and a clear input. CONSTITUTION:A signal D1 is inputted to an input D of the 1st flip-flop (FF) 1 and a clock pulse CLOK is inputted to a clock CK of the FFs 1, 2 and 3. A CLEAR input is connected to a clear terminal CL to clear at once the FFs 1, 2 and 3. A Q2 output of the FF 2 and the Q1 output of the FF 1 are inputted to a NAND gate 4, the Q1 output of the FF 1, the Q2 output of the FF 2 are inputted to a NOR gate 6. The output of the NAND gate 4 in connected to the input of a NAND gate 5. An inverted output Q3 of the FF 3 is connected to the other input of the NAND gate 5. Thus, the output is unchanged even to a short width noise included in the input signal D1 and only a correct input signal change is extracted. |
