发明名称 BI-CMOS LOGIC CIRCUIT
摘要 PURPOSE:To enable a transistor to be driven without increasing any through current component by a method wherein the base current of an NPN bipolar transistor for pull down is driven by using a latch circuit. CONSTITUTION:When the input level changes from 0 to 1, a transistor Q2 is firstly supplied with the base current from input terminal T1 side through another transistor Q5 transiently turned on. Thus, a latch circuit 3 starts inversion; the FET Q5 starts turning off; and another FET Q6 starts turning on. Then, the transistor Q2 is successively driven by bypassing the current to the base of transistor Q2 from an output terminal T2 side through the FET Q6. On the other hand, the other transistor Q1 is turned off through the other FET Q4 since the value of output from a CMOS inverter 2 is reduced to zero. Finally, the collector and base of transistor Q2 are short-circuited through the FET Q6 so that the output from a Bi-CMOS inverter 2 is reduced to the voltage of transistor Q2 in the normal direction.
申请公布号 JPS62254460(A) 申请公布日期 1987.11.06
申请号 JP19860097428 申请日期 1986.04.26
申请人 TOSHIBA CORP 发明人 MATSUI MASAKI
分类号 H01L21/8249;H01L27/06;H03K19/013;H03K19/08;H03K19/0944 主分类号 H01L21/8249
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