发明名称 HIGH SPEED MEMORY DEVICE
摘要 PURPOSE:To access a memory at a high speed by using an address determined in an early time and starting the access of the memory even when the time determined by a part of the address is later than the time determined by other part of the address. CONSTITUTION:The address of a dynamic RAM (DRAM) 10 is multiplexed to a row address and a column address through a multiplexer 5. When the row address and the column address are given to the DRAM 10, by using the fact that the time difference is necessary, an address determined earlier is given to the row address of the DRAM 10, and the address determined later is made into the address to decode to the column address and the memory device selecting signal. When the address for ascessing occurs and a memory device is not selected, the access to the memory is started, and only when the memory device selecting signal is generated by the address determined earlier, the reading or writing of the data are executed. Thus, the memory access can be executed at a high speed.
申请公布号 JPS62252591(A) 申请公布日期 1987.11.04
申请号 JP19860095286 申请日期 1986.04.24
申请人 SEIKO INSTR & ELECTRONICS LTD 发明人 TAKAHASHI TSUNEO
分类号 G06F12/02;G06F12/00;G11C8/00;G11C11/34;G11C11/401 主分类号 G06F12/02
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