发明名称 VARIABLE DELAY CIRUCIT
摘要 PURPOSE:To vary the propagation time of a signal by connecting one control ECL circuit with plural inputs to the output of a signal transmission ECL circuit and supplyind a control binary signal to the other input of the control ECL circuit. CONSTITUTION:One input 12A of the control ECL circuit 12 with plural inputs and that of a control circuit 6 are connected to the output of the signal transmission ECL circuit 12 and that of a semiconductor active circuit 3. The control binary signal is supplied to the other input l2B. An ECL 10 is comprised of resistances R3 and R4, transistors Tr4, Tr5 and Tr6 and a resistance Rp, while an ECL 12 is comprised of resistances R1 and R2, and transistors Tr1, Tr2 and Tr3. And the emitter of the Tr4 is connected to the base of the Tr2. A signal is inputted to the base of the Tr6, and the control binary signal is supplied to the base of the Tr2.
申请公布号 JPS62250713(A) 申请公布日期 1987.10.31
申请号 JP19860093994 申请日期 1986.04.23
申请人 FUJITSU LTD 发明人 YOSHIMURA TATSURO
分类号 H03K5/135 主分类号 H03K5/135
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