| 摘要 |
PURPOSE:To decrease a memory access load and to prevent the increasing in a memory capacity by providing a selector to operate selectively the transferring register of packet transmitting data and a packet completing command generating circuit and sending directly a completing command at the time of a final data transferring completion. CONSTITUTION:In a memory 2, data to be sent as a packet are stored, and a selector 12, first, selects a register 11 by the instruction of a processor 1. At the time of data transfer, when a transmitting request signal is outputted from a transmitting circuit 3 to a direct memory access control circuit 4 and it can transfer the data, a response signal is returned to the transmitting circuit 3, simultaneously, the transmitting data are read byte by byte from the memory 2, enters a bus 5, written to the register 11 once, the data enter the selector 12, are transferred to the transmitting circuit 3 and thereafter, sent successively to a line 302. When the direct memory access control circuit 4 completes to send the prescribed number of the byte (word number) of transmitting data and sends the end signal from a timing circuit 13 to the selector 12, at such a time, a command generating circuit 14 is selected and a transmitting completion command is sent to the transmitting circuit 3.
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