| 摘要 |
PURPOSE:To increase the transmission speed of an external signal by integrating an input function and a multiplexer to reduce the transmission path of the external signal by one stage. CONSTITUTION:An address signal represented as a signal AXi fed from an external terminal is fed to one input of an address multiplexer MX1, that is, gates of P-channel MOSFETQ1 and N-channel MOSFETQ16. The P-channel MOSFETQ2 is provided in parallel with the MOSFETQ1 and the N-channel MOSFETQ15 is connected in series with the MOSFETQ16. A timing signal phixg formed synchronously with the falling of a row address strobe signal RAS is fed to gates of the MOSFETs Q2 and Q15. Thus, the MOSFETs Q1, Q2 and Q15, Q16 act substantially as a CMOS NAND gate circuit.
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