发明名称 PROCESSOR MANAGING SYSTEM
摘要 PURPOSE:To manage a processor in a loop bus by constituting the titled system so that a processor which has received a frame sets an operating state of the own processor by a value being different from that of the time of the previous reception, compares said state with an operating state of the other processor, which has been held in a memory of its processor, and transfers said frame to the next processor. CONSTITUTION:Each processor 1-4 of a processor control system is connected by a loop bus 5, by which a dispersion control type switchboard is constituted. The processor 1 which has received a frame 6 for circulating successively in the bus 5 of this system sets its own operating state to a memory in the frame 6, sets an operating state of other processors 2-4 to a memory 7 in the processor 1, and transfers the frame 6 to the next processor 2. Also, each processor 2-4 sets an operating state in the same way, and each processor 1-4 sets the operating state of its own processor to a value being different from that of the time of the previous reception, compares it with an operating state of its processor, which has been held in memories 8-10, and manages the processors 1-4 in the bus 5.
申请公布号 JPS62248060(A) 申请公布日期 1987.10.29
申请号 JP19860092647 申请日期 1986.04.21
申请人 NEC ENG LTD 发明人 SUGA KAZUMOTO
分类号 G06F15/16;G06F15/177 主分类号 G06F15/16
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