发明名称 PHASED LOCKED LOOP CIRCUIT
摘要 PURPOSE:To seure a phase locked range in a small number of steps by produc ing the control signal based on a sequential comparison method. CONSTITUTION:A frequency comparator 1 compares the frequency of an input signal with that of a VCO 8. A control circuit 12 contains three registers and the 1st and 2nd registers store at first the minimum and maximum values. While the 3rd register stores the calculated medium value of contents between the 1st and 2nd registers. The control data on the VCO 8 is delivered based on the difference between the comparison result of frequencies and the contents of the 3rd register. When the input signal frequency is lower than the output frequency of the VCO 8, the contents of the 1st register are rewritten into those of the 3rd register. Thus the contents of the 1st register are reduced. While the contents of the 2nd register are rewritten to those of the 3rd register if the input signal frequency is higher than the output frequency of the VCO 8. Thus the contents of the 3rd register are increased.
申请公布号 JPS62247624(A) 申请公布日期 1987.10.28
申请号 JP19860080583 申请日期 1986.04.07
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUZUKI YOUSUKE
分类号 H03L7/113;H03L7/10 主分类号 H03L7/113
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