发明名称 PACKET EXCHANGE SYSTEM
摘要 <p>PURPOSE:To shorten the delay time and to improve the exchange efficiency in a packet exchange system by dividing the packet style into a front part for routine information and a rear part for other information for transmission with a time interval and deciding an outgoing circuit. CONSTITUTION:A packet is divided into a front part 381 (PKF) for routine information and a rear part 383 (PKR) for other information. A time filler 382 is put between the PKF and PKR and circuits 34-37 are connected to a switch SW33 and a circuit control part LU32 respectively. The LU32 receives the part PKF from the circuit 34 and selects an optimum outgoing circuit 37 according to the routine information stored in the part PKF to control the SW33 for connection between both circuits 34 and 37. Then the LU32 transmits the PKF to the circuit 37. The filler 382 received from the circuit 34 and the PKF are sent to the circuit 37. Thus the packet delay time is limited just to the value equal to the filler 382, which omits the packet storage and improves the throughput of an exchange.</p>
申请公布号 JPS62247652(A) 申请公布日期 1987.10.28
申请号 JP19860089928 申请日期 1986.04.21
申请人 HITACHI LTD 发明人 HAYASHI KAZUYUKI
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