| 摘要 |
PURPOSE:To enable a high speed response even in an increase in the number of bits for a higher accuracy, by providing a comparator which compares a count value outputted from a D flip flop with a count value outputted from a reversible counter and outputs a control signal when the difference between both the count values exceeds a set value. CONSTITUTION:A reversible counter 1 inputs a positive or negative pulse +P or -P outputted from a PG into an up terminal UP and a down terminal DOWN respectively to count through inverters 4 and 5 in parallel with a reversible counter 6 and outputs a count valve N0 counted at each fixed cycle T preset while being cleared. A comparator 3 receives an input of a count value N1 outputted from a D flip flop 2 to compare both the count values N1 and N2 and outputs a signal LOAD to the reversible counter 6 when the difference between both the count values N1 and N2 exceeds a certain set value to replace the count value N2 of the reversible counter 6 with the current count value N1 as measured at this time.
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