Noise pulse suppressing circuit in a digital system.

摘要

A latch circuit (16) receives and latches an input signal (b) in response to a triggering signal (k) and provides an output signal (c). A counter circuit (13) formed a plurality of D-type flip-flops (12, 14) receives a clock signal (a0) and produces the triggering signal (k) when a predetermined number of trailing or leading edges of clock pulses have been counted. A logic circuit (11) is connected to the latch circuit (16) for generating a reset signal (h) which is applied to the counter circuit to reset same when the latch circuit output and the input signal have the same logic state and for making the counter circuit active when the latch circuit output and the input signal have complementary logic states. No level change in the output signal will occur if the duration of a level change in the input signal is not sufficient to allow the counter circuit to count the predetermined number of edges of clock pulses; thus enabling the suppression of noise pulses of either positive or negative polarity in the input signal and the production of an output signal having edges synchronized on leading or trailing edges of the clock signal.