| 摘要 |
An error-tolerant computer store which includes memory elements (1) addressable in groups, each element storing a binary bit, and an error correction logic (5) is monitored substantially automatically with the aid of an identification signal generator (12), an alarm signal generator (18) and inversion circuits (8, 10) connected to the elements (1) and to the logic (5). The identification signal generator (12) generates an identification signal for marking one of the elements (1) and two of the circuits (8, 10). The identification signal preferably activates the marked circuit (10) for inversion this circuit having its input connected to the marked memory element and its output connected to the error correction logic, the logic is thus being consciously fed with a bit having an incorrect binary valve. If the logic (5) neglects to identify and correct the defective binary bit, the alarm signal generator generates an alarm signal indicating a functional fault in the error correction logic. |
