| 摘要 |
PURPOSE:To reduce the bit width of a main adder and a peripheral circuit by using a cycle selecting the final sum component and the carry component from each multiplication part in the operation of vector operands. CONSTITUTION:An upper-order 4-byte of the final sum component of intermediate register 8-1 or 8-2 to which an output of a carry storage adder CSA is set, is set to a final sum register 14. An upper-order 4-byte of the final carry component of an intermediate register 9-1 or 9-2 is similarly set to a final carry register 15. A multiplexer 16 selects an accuracy guarantee carry of a flip-flop 11-1 or 11-2 to which an output of spill adders 10-1 and 10-2 is set and gives an output. The content of registers 14, 15 and an output of the multiplexer 16 are inputted to a main adder 12' of 32-bit width. |
