发明名称 |
NOISE REDUCTION CIRCUIT |
摘要 |
<p>: A noise reduction circuit for reducing noise in a video signal comprises delay circuits for respectively delaying an output video signal for delay times 2S and H-S (H is one horizontal scanning period and S is a half of one period of the color subcarrier). The outputs of the delay circuits are averaged and the resultant signal is subtracted from an input video signal. The output of the subtraction circuit is attenuated and an addition circuit adds the attenuated output to the input video signal. An edge detection circuit detects an edge of a pattern in the input video signal, and the attenuation factor is set to zero when the pattern edge is detected.</p> |
申请公布号 |
CA1228671(A) |
申请公布日期 |
1987.10.27 |
申请号 |
CA19850491347 |
申请日期 |
1985.09.23 |
申请人 |
HITACHI, LTD. |
发明人 |
KAIZAKI, KAZUHIRO;KUBOTA, SADAO;HARADA, HIROSHI;MATSUURA, SHIGEO |
分类号 |
H04N5/21;H04N9/64;(IPC1-7):H04N9/64 |
主分类号 |
H04N5/21 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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