发明名称 METHOD FOR THE MANUFACTURE OF GATE ELECTRODES FORMED OF DOUBLE LAYERS OF METAL SILICIDES HAVING A HIGH MELTING POINT AND DOPED POLYCRYSTALLINE SILICON
摘要 <p>A method for manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon. The polycystalline silicon is deposited in undoped fashion before the metal silicide and the doping of the silicon is obtained through the production of the source/drain-zones through ion implantation and a subsequent high temperature step. The method permits the problem-free manufacture of polycide-gates with n+- and p+-polysilicon on a chip without increased technological expense. Planarization is facilitated through the thin gate layers. The method is used in the manufacture of highly integrated CMOS-circuits.</p>
申请公布号 CA1228681(A) 申请公布日期 1987.10.27
申请号 CA19850481751 申请日期 1985.05.17
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 NEPPL, FRANZ;SCHWABE, ULRICH;HIEBER, KONRAD
分类号 H01L27/092;H01L21/28;H01L21/3205;H01L21/3215;H01L21/336;H01L21/8234;H01L21/8238;H01L23/52;H01L27/088;H01L29/423;H01L29/43;H01L29/49;H01L29/78;(IPC1-7):H01L29/62 主分类号 H01L27/092
代理机构 代理人
主权项
地址