| 摘要 |
PURPOSE:To operate all plural digital equipments connected in loop synchronously in phase by informing delay correction information from one digital equipment to other digital equipments and allowing each digital equipment to generate a clock based thereupon. CONSTITUTION:The delay time is subject to an exponential value based on the order of connection of slave digital equipments 3-1-, the result is sent to an exchange switch control section 5-1,-via a control line loop controller 4-1,-of the digital equipment 3-l,-at teh post-stage from a cotnrol line loop controller 4-0 of a master digital equipment 3-0 and the result is set to digital itnerface trunks 6-1,-7-1,-as a delay correction. In setting the exponent of the delay time to a F/F 21 of a clock correction circuit, the value is inputted to an address of a ROM 22 and an initial setting value of a counter 23 is outputted from the ROM 22. When the period timing of an exchange switch conrol section 5-1 is inputted to the counter 23 as the initial set, the initial setting value is set to the counter 23 and the counter 23 is counted up by the input clock. |
