| 摘要 |
PURPOSE:To reduce the quantity of hardware at high multiplexing by providing a control memory having an exchange circuit and a feedback loop, a sequential address memory, an address comparison circuit and an output shift register. CONSTITUTION:Address information of the input side highway subjected to exchange connection to each output highway is written in the feedback loop control memory 6 and the address information is shifted so as to be circulated in the shift register of the control memory 6. The address information in the control memory 6 is outputted in parallel and the address information of a sequential address memory 8 is compared altogether at each shifting and a write signal is sent from an address comparison circuit 9 only to an address where both the address information is coincident. An output shift register 10 writes a corresponding input data only to an address receiving a write signal. Thus, the hardware at high multiplexing is saved.
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