| 摘要 |
In a graphic display apparatus having a digital differential analyzer (DDA), a chrominance data stored in a register is written in an area of a bit map memory defined by coordinates generated from DDA by a write control circuit in response to ARDY signal. A first flip-flop is reset by a busy signal from the write control circuit and is set by a load signal. When the first flip-flop is in a reset state, a first gate produces PRDY signal requesting a microprocessor to load the chrominance data in the register in response to RDY signal indicating completion of a coordinate setting operation from DDA. When the first flip-flop is in a set state, a second gate generates CRDY signal in response to RDY signal. CRDY and RDY signals are supplied to a selector which selects one of them due to a second flip-flop for switching a line processing mode and a raster operation mode, and supplies the selected signal to the write control circuit to thereby perform write operation.
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