| 摘要 |
<p>PURPOSE:To reduce the number of input terminals, by providing an edge detection circuit which detects the edge of a program start signal, and a frequency dividing circuit which frequency-divides a master clock. CONSTITUTION:A program synchronous circuit is constituted of an edge detection circuit 55, a frequency dividing circuit 56, latch circuits 60-64, a frequency dividing counter 65 of two bits, a program counter 66, and a program storage circuit 67. The synchronous circuit detects the leading edge of a program start signal 72 at the edge detection circuit 55, and synchronizes the frequency dividing circuit 56, and generates a clock synchronized with the program start signal 72. Furthermore, it detects the trailing edge of the program start signal 72, and starts a program by controlling the program counter 66. In this way, it is possible to generate the clock and to start the program only by the program start signal 72, and a master clock 74, and to reduce the number of the input terminals.</p> |
