| 摘要 |
<p>PURPOSE:To make writing by noise, or the runaway of a processor unit impossible by making valid the write on the allocated address of a EEPROM only when a normal sequence is written on a designated address. CONSTITUTION:A latch circuit 3, a sequence comparison circuit 4, a normal sequence generation circuit 5 and a gate circuit 6 are added to a CPU2 which controls the write and a read to the EEPROM1. The sequence comparison circuit 4 compares the sequence of the normal sequence generation circuit 5 with the sequence at the latch circuit 3 latched by a write operation, and when both are coincided, it outputs a permission signal through a write permission signal line 12. In this way, it is possible to write a data from the CPU2 to the EEPROM1.</p> |
