| 摘要 |
PURPOSE:To attain the fast and continuous readout of data, by making unnecessary a memory access wait time at the switching time of a memory bank from the final stage to the first stage. CONSTITUTION:A preceding address larger by one than the present address outputted from a data processor is sent out from an address incrementor 3, and address selectors 101, 102, and 103, supply addresses on one sides to memory banks 102, 202, and 302, by the signal from a preceding address select signal generator 4. A continuous address deciding unit 30 decides whether the address is a continuous address or not, and a pulse extendor 21 generates a memory wait time by a decision signal at a time when the address is not the continuous one. The selection of the bank is terminated while the signal is outputted from the pulse extendor 21.
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