发明名称 CENTRAL PROCESSING UNIT
摘要 <p>PURPOSE:To raise the processing efficiency of a processor by varying an operation clock frequency by a control from an arbitration control circuit for controlling a main processor and a subprocessor. CONSTITUTION:A clock control circuit 43 varies a generation frequency by a control from an arbitration control circuit 3. That is to say, when a subprocessor 2 does not operate but only a main processor 1 is operating, the highest frequency by which the device 1 can operate is generated. In this state, when it is informed that the device 2 is started, a frequency being suitable thereto is generated. In this way, the efficiency of a processing of a central processing unit constituted of the main processor and the subprocessor is raised.</p>
申请公布号 JPS62243060(A) 申请公布日期 1987.10.23
申请号 JP19860088828 申请日期 1986.04.16
申请人 NEC CORP 发明人 MATSUBARA KIYOTAKA
分类号 G06F15/16;G06F1/06;G06F15/177 主分类号 G06F15/16
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