| 摘要 |
PURPOSE:To improve the capacity of access processing by providing the titled system with a controller for calculating the N groups of addresses of a time switch control memory and their contents from various information of N-times access and updating said memory between said memory and a processor. CONSTITUTION:When an input side time slot and an output side time slot are determined in case of exchange of N-times access, the k-th writing address WAk and writing date WDk of a time switch control memory CM are shown as follows when it is defined that the band width for a reference transmission speed is N, the least time slot numbers of highways on the input and output sides are Oo, Io and the intervals of adjacent time slots on respective highways of the input and output sides are m1, m2. Namely, WAk=Oo+m1k and WDk=Io+ m2k (0<=k<=N-1). A control device CONT calculates the data WAk, WDk and updates the memory CM. Since a processor PROC supplies only the information such as the intervals m1, m2 and the numbers Oo, Io, its load is reduced.
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