| 摘要 |
PURPOSE:To reduce area loss and to improve reliability by providing a row read line and a column read line corresponding one by one to a spare bit line. CONSTITUTION:The spare bit line 3 corresponds one by one to a spare row information read line 13 and a spare column information read line 14, both the spare row information read line 13 and a row information read line 6 having information selected by a selector 1 by using a row selection signal 4 from a substantial bit line 2 are inputted to a row parity generation circuit 11 to generate the row parity. A switch circuit of the spare bit line to replace the bit line is controlled at an address generating a row selection signal selecting the substantial bit line to be replaced. Thus, the provision of lots of fuses is not required between the spare bit line and row/column selection signals, the loss of the chip area is less and high reliability is obtained.
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