发明名称 TEST CIRCUIT FOR DECODER
摘要 PURPOSE:To shorten the detecting time of a defect due to disconnection by adding a circuit for turning all decoder input signals to '1' and a circuit for detecting and outputting a state that all test mode switching inputs and decoder output signals are '1' to a decoder. CONSTITUTION:When '0' is inputted to a test mode switching input T-IN (normal mode), decoder inputs 5-12 are turned to encoded signals of data inputs 1-4 and the inversional signals of the data inputs 1-4 to act as decoders. When '1' is inputted to the test mode switching input T-IN (test mode), all the decoder inputs 5-12 are turned to '1' independently of the values of the data inputs l-4. Since all transistors (TRs) in the decoder are turned on in the test mode, all decoder outputs A-G are turned to '1' if the wiring in the decoder is not disconnected. At that time, '1' is outputted from an output T-OUT in the test mode.
申请公布号 JPS62242423(A) 申请公布日期 1987.10.23
申请号 JP19860086763 申请日期 1986.04.14
申请人 NEC CORP 发明人 MATSUMOTO TAKESHI
分类号 H03M7/00 主分类号 H03M7/00
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