发明名称 MAXIMUM LIKELIHOOD DECODER
摘要 PURPOSE:To attain the maximum likelihood decoding with excellent error rate characteristic and simple hardware constitution by applying region decision and compressing location information on constration of a reception point. CONSTITUTION:When signals I, Q having factor to deterioration such as noise and sent by the orthogonal amplitude modulation are inputted to a decoder, the constration is divided into small regions in a decision circuit 11 and which region a reception point (I, Q) exists is identiied and the region information is stored in a memory 12. Then the path likelihood is obtained only to eight nearby points decided definitely from the region to which the reception point belongs, the addition/comparison/ selection are processed (14) from the path likelihood and the state likelihood subject to normalization 16, the remaining path is stored (15) and the state likelihood obtained newly is normalized. Then the remaining path information is used, the path is stopped and reversed by the stop length, the tracing state of the decoder and its output are estimated (17) at time, a low-order 3-bit is decoded (18) at first and the high-order 4-bit is decoded (18) from the decoded output and the area information of the memory 12.
申请公布号 JPS62243431(A) 申请公布日期 1987.10.23
申请号 JP19860085983 申请日期 1986.04.16
申请人 HITACHI LTD;HITACHI DENSHI LTD 发明人 KOBAYASHI NAOYA;ONISHI MAKOTO;KOKURYO GARO
分类号 H03M13/00;H03M13/23;H04L27/02;H04L27/34 主分类号 H03M13/00
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