| 摘要 |
<p>PURPOSE:To transfer a data at a high speed without being awaited in order to obtain a bus from a processor at every data transfer of once, by transferring the data by synchronizing each DMAC which is provided in accordance with each memory. CONSTITUTION:A host processor 1 and a peripheral processor 2 are connected by a transfer synchronizing control line and a data bus 4. The processor 1 sets a direct memory access controller DMAC 13, and writes a necessary data to a register 26 belonging to the processor 2. As a result, the processor 2 sets a DMAC 23, based on the contents which are written in the register 26. When the DMAC 23 which is set executes a transfer request to the DMAC 13, the DMAC 13 obtains a bus of the host side and executes a transfer request to the DMAC 23. In such a way, the DMAC 23 obtains a bus of the peripheral side, and a data transfer is started.</p> |
