| 摘要 |
An integrated circuit memory (10) has row lines (RL); select lines (SL); output lines (BL); and memory cells (14) arranged in pairs (17). Each pair of memory cells (14) has common outputs (32) coupled to a selected one of the output lines (BL) and common address inputs (31) coupled to a selected one of the row lines (RL). Ambiguity of which memory cell (14) of the pair (17) of memory cells (14) is to be selected, both being coupled to a selected one of the row lines (RL) and a selected one of output lines (BL), is determined by two selected select lines (SL) coupled thereto. A first decoder (100,120), responsive to an input address (A0-Am-1), enables a selected one of the row lines (RL), and a second decoder (100,130,140), responsive to the row lines and to the input address, enables a selected one of the select lines (SL) which corresponds to pairs (17) of memory cells (14) with an enabled row line (RL). |
