发明名称 VITERBI DECODER
摘要 PURPOSE:To easily deal with a punctured system which is increased in encoding rate by setting one integrated circuit in normal mode and constituting a viterbi, decoder, and cascading bus memory circuits of plural integrated circuits when path memory length is increased. CONSTITUTION:An ACS circuit 1, a path memory circuit 2, a path selecting circuit 3, and selectors 4 and 5 are IC-implemented and the selector 4 selects and outputs a path select signal from the ACS circuit 1 when set in normal mode with an operation mode setting signal and the output signal of the path memory circuit 2 when set in path memory mode. The selector 5, on the other hand, selects and outputs the path select signal outputted by the ACS circuit 1 to the path memory circuit 2 when set in normal mode and a path select signal from another viterbi decoder when set in path memory mode. When the path memory length is increased, path memory circuits 2 of plural integrated circuits are cascaded, one integrated circuit is set in normal mode while others are set in path memory mode, and the path memory circuits 2 of the respective integrated circuits are cascaded.
申请公布号 JPS62241437(A) 申请公布日期 1987.10.22
申请号 JP19860058172 申请日期 1986.03.18
申请人 FUJITSU LTD 发明人 YAMASHITA ATSUSHI;KATO TADAYOSHI;MORIWAKE MASARU
分类号 H03M13/23 主分类号 H03M13/23
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