发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To performs the dereference processing at high speed by introducing a dereference flag indicating the prefetch of data and using the inspection result of the tag part of a data processing block and the state of the dereference flag. CONSTITUTION:A branch control block 7 controls so as to invalidate a mistake occurrence signal from a cache memory 2 and an address converting buffer 4 according to the inspection result of the tag part by the data processing block 5 and the state of the dereference flag 6. Namely, when the dereference flag 6 is turned on and when the inspection result of the tag part by the data processing block 5 is pointer data and when the dereference flag 6 is turned off, the mistake generating signal is effective and during other period, it is invalid. by neglecting this mistake occurrence signal, a trap to an unnecessary swap processing or an address converting processing resulting from a memory access in which a value part such as integer data generated during the data prefetch processing is treated as a logical address.
申请公布号 JPS62242255(A) 申请公布日期 1987.10.22
申请号 JP19860085190 申请日期 1986.04.15
申请人 NEC CORP 发明人 HABATA SHINICHI
分类号 G06F9/44;G06F12/08;G06F12/10 主分类号 G06F9/44
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