| 摘要 |
1. A modular integrator capable of integrating m signals, comprising at least p bits M0 to Mp-1 under the control of a signal constituted by two bits Y1 and Y0 , characterized in that it comprises at least one elementary operator (1) having a first register RI (102) for receiving the successive signals to be integrated, a second register X (103) for receiving a recycling signal including n bits (n =< p + integer part of [log2 m]) and for delivering the integrated signal constituted by n bits I0 to In-1 , decoding circuits D (112 to 117) for receiving the control signal, an adder (110) equipped with a carry-over input for receiving the control bits Y1 and with a carry-over output, and a circuit S (111) for delivering the recycling signal obtained according to the Booth algorithm between the signal to be integrated, the recycling signal obtained by means of the signal to be integrated on the one hand and of the recycling signal obtained during the preceding clock period on the other hand, these two signals being combined under the control of the control signal (Y1 , Y0 ). |
