| 摘要 |
PURPOSE:To simplify the constitution of a demultiplexing circuit for a multiplex signal and a data transmitting speed circuit by performing both data separation and speed conversion by a single memory. CONSTITUTION:The 1st separating and speed converting circuit 17 has eight shift registers S1-S8 corresponding to eight terminal devices T1-T8. The respec tive shift registers S1-S8 are provided as a memory for data separation and speed conversion and connected between an input highway 12 and input lines 3phia-30h of the 1st-the 8th terminal devices T1-T8. The 1st multiplexing and speed converting circuit 21 has shift registers 35-35h connected between output lines 34a-34h of the terminal devices T1-T8 and a common output high way 12a. Further, strobe signal input terminals of the respective shift registers 35a-35h are connected to a common write strobe signal line 41.
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