| 摘要 |
<p>An interrupt control method in a multiprocessor system wherein a plurality of processors (21, 31, 41) and an interface circuit (10) that generates interrupt are connected to a bus of a single system. Using particular address spaces (Addr1, Addr2, Addr3) as interrupt addresses, the processors select mask bits that correspond to said address spaces, store said mask bits in the registers (24, 34, 44) of said processors, and a bus cycle generating circuit in the interface circuit (10) occupies a bus upon receipt of an interrupt signal, indicates its own cause of interrupt, and writes a bit corresponding to said address space onto an address bus. The processors (21, 22, 23) recognize the interrupt from bits of said addresses corresponding to the address spaces (Addr1, Addr2, Addr3) and from the mask bits of said registers (24, 34, 44).</p> |
